Journal papers

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  • 139 D. S. Lee, S. Kang, K.-C. Kang, J.-E. Lee, J. H. Lee, K.-J. Song, D. M. Kim, J. D. Lee and B.-G. Park "Fabrication and Characteristics of Self-Aligned Dual-Gate Single-Electron Transistors" IEEE Trans. Nanotechnology, vol. 8, no. 4, pp. 492-497, 2009-07
  • 138 S. R. Park, K. Y. Kim, C. Choi, K.-J. Song, J.-H. Park, K. Jeon, S. Lee, T. Y. Kim, J. E. Lee, S, Lee, S. Park, J. Jang, D. M. Kim and D. H. Kim "Comparative Study on Program/Erase Efficiency and Retention Properties of 3-D SONOS Flash Memory Cell Array Transistors : Structural Approach from Double-Gate FET and FinFET to Gate-All-Around FET" Journal of Korean Physical Society, vol. 54, no. 5, pp. 1854-1861, 2009-05
  • 137 K. Jeon, S. Lee, J.-H. Park ,C. Choi, K.-J. Song, S. R. Park, T. Y. Kim, J. E. Lee, S. Park, S. Lee, J. Jang, D. H. Kim, and D. M. Kim "Optical Charge Pumping Method for Extracting the Energy Level of Interface States in Program/Erase Cycled SONOS Flash Memory Cell and Its Program Time Dependence" Journal of Korean Physical Society, vol. 54, no 5, pp. 1862-1867, 2009-05
  • 136 K. S. Roh, S. Park, K.-J. Song, J.-H. Park, S. Lee, C. Choi, K. Jeon, S. R. Park, T. Y. Kim, J. E. Lee, S. Lee, J. Jang, D. H. Kim, and D. M. Kim "Lateral Trapped Charge Profiling Based on the Extraction of Flat Band Voltage by using the Optical Substrate Current in Charge Trapping Flash Memory Cells" Journal of Korean Physical Society, vol. 54, no. 5, pp. 1848-1853, 2009-05
  • 135 J.-H. Park, K. Jeon, S. Lee, S. Kim, S. Kim, I. Song, C. J. Kim, J. Park, Y. Park, D. M. Kim, and D. H. Kim "Extraction of Density of States in Amorphous GaInZnO Thin Film Transistors by Combining an Optical Charge Pumping and Capacitance-Voltage Characteristics" IEEE Electron Device Letters., vol. 29, pp.1292-1295, 2008-12
  • 134 K. Jeon, C. Kim, I. Song, J. Park, S. Kim, S. Kim, Y. Park, J.-H. Park, S. Lee, D. M. Kim, and D. H. Kim "Modeling of amorphous InGaZnO thin-film transistors based on the density of states extracted from the optical response of capacitance-voltage characteristics" Appl. Phys. Lett., vol. 93, pp. 182102, 2008-11
  • 133 S. Kang, D. H. Kim, I.-H. Park, J.-H. Kim, J.-E. Lee, J. D. Lee, and B.-G. Park "Self-Aligned Dual-Gate Single-Electron Transistors" Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 3118-3122, 2008-04
  • 132 S. H. Seo, G.-C. Kang, K. S. Roh, K. Y. Kim, S. Lee, K.-J. Song, C. M. Choi, S. R. Park, K. Jeon, J.-H. Park, B.-G. Park, J. D. Lee, D. M. Kim, and D. H. Kim "Dynamic Bias Temperature Instability-like Behaviors under Fowler-Nordheim Program/Erase Stress in Nanoscale Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) Memories" Appl. Phys. Lett., vol. 92, pp. 133508-133510, 2008-04
  • 131 J.‐H. Ahn, J.‐Y. Kim, M.‐L. Seol, D. J. Baek, Z. Guo, C.‐H. Kim, S.‐J. Choi, and Y.‐K. Choi "A pH sensor with a double‐gate silicon nanowire field‐effect transistor" Applied Physics Letters, vol. 102 no. 8 pp. 083701, 2013-02
  • 130 S. W. Kim, K. S. Roh, S. H. Seo, K. Y. Kim, G. C. Kang, S. Lee, C. M. Choi, S. R. Park, J. H. Park, K. C. Chun, K. J. Song, D. H. Kim and D. M. Kim "Extraction of interface states at emitter-base heterojunctions in AlGaAs/GaAs heterostructure bipolar transistors using sub-bandgap photonic excitation" Microelectronics Reliability, vol 48, issue 3, pp. 382-388, 2008-03
  • 129 J. P. Duarte, S.‐J. Choi, D.‐I. Moon, J.‐H. Ahn, J.‐Y. Kim, S. Kim, and Y.‐K. Choi "A Universal Core Model for Multiple‐Gate Field‐Effect Transistors. Part II: Drain Current Model" IEEE Transactions on Electron Devices, vol. 60 no. 2 pp. 848–855, 2013-02
  • 128 S. H. Seo, S. W. Kim, J.-U. Lee, G.-C. Kang, K. S. Roh, K. Y. Kim, S. Lee, C. M. Choi, K.-J. Song, S. R. Park, J.-H. Park, K. Jeon, D. M. Kim, and D. H. Kim "Investigation of Channel Width Dependence of CHEI Program / HHI Erase Cycling Behavior in Nitride-based Charge-Trapping Flash (CTF) Memory Devices" Journal of Korean Physical Society, vol. 52, pp. 481-486, 2008-02
  • 127 J. P. Duarte, S.‐J. Choi, D.‐I. Moon, J.‐H. Ahn, J.‐Y. Kim, S. Kim, and Y.‐K. Choi "A Universal Core Model for Multiple‐Gate Field‐Effect Transistors. Part I: Charge Model" IEEE Transactions on Electron Devices, vol. 60 no. 2 pp. 840–847, 2013-02
  • 126 S.‐J. Choi, P. Bennett, K. Takei, C. Wang, C. C. Lo, A. Javey, and J. Bokor "Short‐Channel Transistors Constructed with Solution‐Processed Carbon Nanotubes." ACS nano, vol. 7. no. 1. pp. 798-803, 2012-12
  • 125 J.-G. Lee, D. H. Kim, J. G. Lee, D. M. Kim and K.-S. Min "A compact HSPICE macromodel of resistive RAM" IEICE Electron. Express, vol. 4, no. 19, pp. 600-605, 2007-10
  • 124 S.‐J. Choi, C. Wang, C. Chi Lo, P. Bennett, A. Javey, and J. Bokor "Comparative study of solution‐processed carbon nanotube network transistors" Applied Physics Letters, vol. 101 no. 11 pp. 112-104, 2012-11
  • 123 D. M. Kim, D. H. Kim, S. Y. Lee "Characterization and modeling of temperature-dependent barrier heights and ideality factors in GaAs Schottky diodes" Solid-State Electronics, vol. 51, pp. 865-869, 2007-01
  • 122 C. H. Lee, S. W. Kim, J. U. Lee, S. H. Seo, G.-C. Kang, K. S. Roh, K. Y. Kim, S. Y. Lee, D. M. Kim, and D. H. Kim "Design of a robust analog-to-digital converter based on complementary SET/CMOS hybrid amplifier" IEEE Trans. Nanotechnology, vol. 6, no. 6, 2007-11
  • 121 M.‐L. Seol, J.‐H. Ahn, J.‐M. Choi, S.‐J. Choi, and Y.‐K. Choi "Self‐aligned nanoforest in silicon nanowire for sensitive conductance modulation." Nano letters, vol. 12 no. 11 pp. 5603–5608, 2012-10
  • 120 J. U. Lee, K. S. Roh, G. C. Kang, S. H. Seo, K. Y. Kim, S. Lee, K. J. Song, C. M. Choi, S. R. Park, J. H. Park, K. C. Jeon, D. H. Kim, and D. M. Kim "Optical capacitance-voltage characterization of charge traps in the trapping nitride layer of charge trapped flash memory devices" Appl. Phys. Lett., vol. 91, ,pp. 223511, 2007-11